1. Field of the Invention
The present invention relates to a data processor with a cache system and a data access method therefor, and in particular, to a data processor with a cache system which can execute high speed processing of a CPU after the occurrence of an abnormality in transferring data during reading of a plurality of data from a memory system to the cache when the cache misses, and to a data access method for a data processor.
2. Description of the Related Art
FIG. 1 is a block diagram illustrating construction of a peripheral portion of the CPU and cache of the invention disclosed in Japanese Patent Application No. 2-10839 (1990) which is an example of a conventional data processor with a cache system.
In this prior art, there is shown a construction where a memory system 3 is only accessed by a block transfer mode which transfers multiple data from the memory system 3 in the case where a cache 2 misses after the CPU 1 accesses the cache 2 to read a specific item of data therefrom.
Reference numerals in FIG. 1 designate the following elements: 1, CPU; 2, cache; 3, memory system; 6, system bus buffer; 8, multiplexer; 9, OR logic circuit with inputs and output active low; and SB, system bus.
The system bus buffer 6 is provided as a common interface between the CPU 1 and cache 2 and the system bus SB.
Signals transmitted and received among the CPU 1 and cache 2 and the system bus buffer 6 are roughly divided into control signals, address signals and data signals.
A control signal SCa is used as a duplex common control signal among the CPU 1, the cache 2 and the system bus buffer 6; while, a control signal SCb1, which is used only in the case where the CPU 1 is a bus master, is used as a duplex signal between the CPU 1 and the cache 2 and as a duplex signal between the CPU 1 and the system bus buffer 6. Control signal SCb14, inputted to the CPU 1, is a signal outputted from the OR logic circuit 9 which receives both a ready signal SCb12 outputted from the cache 2 and a ready signal SCc12 outputted from the memory system 3 via the system bus buffer 6. SCb14 is used to indicate the end of data transfer to the CPU 1.
Incidentally, the ready signal SCb12 is used as a cache hit signal when the cache 2 hits.
A control signal SCc15 is an abnormal bus access signal which indicates that an abnormal bus access has occurred, such as an abnormality in which the read-access operation is unable to be performed when a read-access is executed to the memory system 3. The signal SCc15 is outputted from the system bus buffer 6 to the CPU 1 in the same way as the ready signal SCc12.
Signal SCe is an operation allowance signal outputted from the cache 2 to the memory system 3. Signal SCf is used to control the CPU 1 from the cache 2 in order to stop the CPU 1 from executing a new bus cycle so that the address signal or bus control signal can not be started.
An address signal AD1 is transmitted from the CPU 1 to both the cache 2 and the system bus buffer 6. An address signal AD2, which is used only when the CPU 1 is a bus master, is transmitted from the CPU 1 to both the cache 2 and a multiplexer 8. Address signal CAD2, which is used only when the cache 2 is the bus master, is transmitted from the cache 2 to the multiplexer 8.
In response to a multiplexer control signal SC2 outputted from the cache 2, the multiplexer 8 selects either the address signal AD2 or CAD2 to output as an address signal AD3 to the system bus buffer 6.
Incidentally, a data signal SD is used as a duplex common signal among the CPU 1, the cache 2 and the system bus buffer 6; and .phi. designates a clock signal which is transmitted to both the CPU 1 and the cache 2.
Operation will now be described for the case where the cache 2 hits and misses when the CPU 1 uses the cache 2 in a conventional cache systems constructed as described above, with reference to the timing charts of FIG. 2 and FIG. 3. In the following description, assuming that the CPU 1 attempts to read data for the cache 2, the control signal SCa is assumed to activate the cache 2.
In the CPU 1, one bus cycle consists of four timings T1 through T4 (designated by T1234 in FIG. 2) of the clock .phi. as shown in FIG. 2. When the CPU 1 accesses to read a single data, this operation is completed in two bus cycles with no wait.
FIG. 2 is a timing chart illustrating the execution of a no wait operation in the case where the cache 2 hits when the CPU 1 attempts to read a single data from the cache 2.
In FIG. 2, [CPU 1 .fwdarw.] designates signals outputted from the CPU 1. The address signal AD1 (address value "m") designates the high order 28 bits of address output by the CPU 1. The address signal AD2 (address value "n") designates the low order 2 bits of the address.
Control signals SCb10, SCb11 are both included in the control signal SCb1. The former signal SCb10 is asserted over one bus cycle beginning at a rising edge of timing signal T1 (hereinafter referred to as T1 .uparw.) in order to indicate that the CPU 1 is starting a bus access for the external device. The latter signal SCb11 expects specific data and starts to be asserted after the rising edge of timing signal T4 during a bus cycle at which the control signal SCb10 is asserted.
In FIG. 2, [cache 2 .fwdarw.] designates signals outputted from the cache 2. When the cache 2 hits, the ready signal SCb12 (showing that the cache 2 hits), the data signal SD, the control signal SCe (which requests allowance of operation for the memory system 3), the control signal SCf (by which the cache 2 makes the CPU 1 stop initiation of new bus cycles), and the signal SC2 (which controls the multiplexer 8) are outputted.
In this case, because the cache 2 is not the bus master, the signal SC2 which controls is the multiplexer 8 and the control signal SCe which requests allowance of operation for the memory system 3 are both in the negated, or non-asserted, state.
Now will be described operation of a conventional data processor when the cache 2 hits in the case where the CPU 1 attempts to read from the cache 2, and FIG. 2 is a timing chart thereof.
The bus cycle in which the signal SCb10 is asserted by the CPU 1 and in which outputs of the next address signals AD1, AD2 are started is called state SR1 of cache 2. During the state SR1 of cache 2, it is determined whether the cache 2 hits or not. As a result of this determination, in the case where the cache 2 hits, during the next bus cycle, called state SR2H, the ready signal SCb12 (being the cache hit signal) is asserted. The ready signal SCb12, which is given through the OR logic circuit 9 to the CPU 1 as the ready signal SCb14, and the data signal SD are asserted so that data is transferred from the cache 2 to the CPU 1.
Next will be described below operation procedures of a conventional data processor in the case where four words of data including a single data word, are requested to be read-accessed by the CPU 1 and the cache 2 misses.
When the cache 2 is determined to have missed, the four words of data (including the single data which has been accessed by the CPU 1 for a read) are read from the memory system 3, connected to the system bus SB, by a round robin method.
This operation is shown in the timing chart of FIG. 3 showing operation in the case where the cache misses. Incidentally, each of the control signals in FIG. 3 is low-active.
First, during the state SR1 in which read-access has been requested by the CPU 1, when the cache 2 is determined to have missed, the ready signal SCb12 (showing cache 2 hits) is not asserted after the next bus cycle (called state SR2M) but the control signal SCe for the system bus buffer 6 is asserted, and the read operation is activated for the memory system 3.
The cache 2 asserts the multiplexer control signal SC2 for the multiplexer 8, and outputs the address signal CAD2 (address value "n" accessed by CPU 1) from the cache 2 as the address signal AD3 to the system bus buffer 6. For this address, the ready signal SCc12, which has been transferred from the memory system 3, is inputted to the cache 2, while it is inputted as the ready signal SCb14 from the OR logic circuit 9 to the CPU 1.
At this time, in the present bus cycle (called state SR2M), the control signal SCf, which stops the CPU 1 from activating a new bus cycle, is asserted.
When both the ready signal SCc12 and data signal SD outputted from the system bus buffer 6 are asserted, the CPU 1 and cache 2 are simultaneously sampled at the timing T3 .dwnarw. to read data. In addition, at this time, in the case where a read response from the memory system 3 delays, it is possible to delay the data-read of the CPU 1 and the cache 2 by delaying assertion of the ready signal SCc12. The CPU 1 negates (de-asserts) the control signal SCb11, terminating the read-access of the data to be accessed, that is, the single data to which read-access has been requested.
At this time point, the control signal SCf outputted from the cache 2 has already been asserted as described above. Then, the next bus cycle is not newly asserted and both the address signals AD1 and AD2 are holding their previous values "m" and "n" respectively. During that time, the CPU 1 can continue execution of its internal processing, such as pipeline processing.
After that, while the cache 2 sequentially increments the address signal CAD2 in the order of "n+1", "n+2", "n+3", respectively, by one bus cycle by the round robin method, it accesses the memory system 3 to read data of the second word, third word, and fourth word corresponding to each value.
Incidentally, while the cache 2 is outputting the value "n+3" as the address signal CAD2, it negates the control signal SCf so that the CPU 1 can execute a usual access from the next bus cycle, and negates the control signal SCe to stop the output of the address signal CAD2 after reading of data of the fourth word.
The operation of the invention of the above-mentioned Japanese Patent Application No. 2-10839 (1990) is described above.
Referring now to the timing chart of FIG. 4, an example of the case where the memory system 3 has a parity check function, for example, and when the cache 2 misses to read data of four words by the round robin method will be given. Also, explanation will be given on the operation in the case where the parity check result of data outputted from the memory system 3 indicates that there has been an error at the time of accessing the first word determined by the address signal AD1 ("m") (outputted from the CPU 1) and CAD2 ("n") (outputted from the cache 2).
As shown in the timing chart of FIG. 4, in the case where an error occurs, the data outputted from the memory system 3 is given to the CPU 1 and cache 2 with the abnormal bus access signal SCc15 and ready signal SCc12 outputted from the bus buffer 6 being asserted.
The data accessed by the CPU 1 according to the assertion of both of the signals SCc15 and SCc12 as aforementioned is read by the cache 2 at the same time. Predetermined processing must be executed for abnormal bus access at the time when the CPU 1 detects the abnormal bus access after the data is made ineffective.
On the other hand, the cache 2 determines that the data of the first word is an abnormal bus access, and the data of four words read by block transfer mode must be made ineffective without being stored in the cache 2. In the aforementioned conventional example, however, the cache 2 successively dummy-reads all of the requested data even when the abnormal bus cycle signal is inputted at the first word. Therefore the cache 2 sequentially increments and outputs the address signal CAD2 in the order of "n+1", "n+2", "n+3" by the round robin method. During this time, the CPU 1 cannot excuse abnormal bus access processing as the cache 2 is continuing to assert the control signal SCf thus stopping the initiation of new bus cycles.
Thus, as described above, we see the effect of an abnormal bus access response from the memory system 3 in a conventional data processor. In the case where the CPU 1 reads the first data when the CPU 1 accesses to read a single data for the cache 2 and the cache 2 misses, the CPU 1 cannot return to normal operation until the cache 2 finishes dummy-reading the remaining three words of the block transfer of every four words. In addition, there are various problems such as the case in which the cache 2 dummy-reads ineffective data of the remaining three words as the caches 2 is undergoing a block transfer, and thereby bus cycles are consumed uselessly.